A simulation framework for hierarchical Network-on-Chip systems

Today, even the simplest laptop processor has at least four cores and a graph-ics card containing tens of cores. It is not hard to find more performance-oriented processors with hundreds of cores, and it is expected to see proces-sors with thousands of cores in the not very far future.In these and future processors, the design of the interconnection networkbetween the cores and the memory subsystem is a key design aspect.Simple topologies like buses or rings provide great efficiency, but do notscale as good as meshes once the number of cores increases. We explorethe use of hierarchical network designs as an alternative, where differenttopologies are stacked in a single network. The lowest layers use rings orbuses, taking advantage of locality, while other layers use meshes or morecomplex topologies.To fully explore these and other chip multiprocessor design aspects, webuild an interconnection network simulator that is capable of simulating ar-bitrary hierarchies of multiple network topologies. We propose using param-eterizable automata as traffic sources, as a trade-off between full processorsimulation and simulation using purely random traffic. By altering the au-tomaton high-level parameters, changes in the processor workload can besimulated, such as the expected average memory traffic, the locality of thememory accesses, the additional traffic caused by different cache coherencyprotocols, etc.